There is a liquid crystal display device including a pixel circuit provided with a photosensor. Efforts are now made to apply such the liquid crystal display device to fingerprint authentication, touch panels, etc.
FIG. 6 shows (i) a configuration of a display region included in such the display device described in Patent Literature 1 and (ii) a block diagram of a circuit for driving the display region.
In the display region, a pixel 18, which constitutes an array, includes a sensor circuit 10, in addition to a display circuit including a liquid crystal capacitor CLC, an auxiliary capacitor C2, a TFT M4, etc. The sensor circuit 10 includes an amplifier TFT M1 of n-channel type, a photosensor D1, and a capacitor C1.
In the display circuit, a gate of the TFT M4 is connected with a gate line GL, and a source of the TFT M4 is connected with a data line 6′. The liquid crystal capacitor CLC is formed between (i) a pixel electrode connected with a drain of the TFT M4 and (ii) a common electrode to which a common voltage VCOM is applied. The auxiliary capacitor C2 is formed between the pixel electrode and a common wire TFTCOM.
The gate line GL and the common wire TFTCOM are driven by a gate driver 15, whereas the data line 6′ is driven by a source driver 14.
In the sensor circuit 10, a cathode of the photosensor D1 and one end of the capacitor C1 are connected with each other, and a gate of the amplifier TFT M1 is connected with a point at which the photosensor D1 and the capacitor C1 are connected with each other. A drain of the amplifier TFT M1 is connected with the data line 6′, and a source of the amplifier TFT M1 is connected with a sensor output wire 6. The data line 6′ is driven by a sensor read-out driver 17 via a switch (not illustrated) during a sensor driving period, which is not included in a data signal writing period. A voltage of the sensor output wire 6 is read by the sensor read-out driver 17.
An anode of the photosensor D1 is connected with a reset wire RST, and the other end of the capacitor C1 is connected with a row selection wire RS. The reset wire RST and the row selection wire RS are driven by a sensor row driver 16.
FIG. 7 shows a concrete configuration of the sensor circuit 10 in detail. The drain of the amplifier TFT M1 is connected with the data line 6′. Further, the drain of the amplifier TFT M1 is supplied with a voltage Vdd from the sensor read-out driver 17 during the sensor driving period. The source of the amplifier TFT M1 outputs a sensor output voltage Vout to the sensor output wire 6. Between the gate and the drain of the amplifier TFT M1, a capacitor Cagd is formed. Between the gate and the source of the amplifier TFT M1, a capacitor Cags is formed.
The photosensor D1 is constituted by a diode-connected TFT 101. The photosensor D1 includes (i) an anode A, which is constituted by connection of a gate and a drain of the TFT 101, and (ii) a cathode K, which is constituted by a source of the TFT 101. The anode A is supplied with a voltage Vrst from the reset wire RST. Between the anode A and the cathode K, i.e., between the gate and the source of the TFT 101, a capacitor Cdgs is formed.
The capacitor C1 has a capacitor value Cst. The other end of the capacitor C1 is supplied with a voltage Vpulse1 from the row selection wire RS.
The gate of the amplifier TFT M1, the cathode of the photosensor D1, and the one end of the capacitor C1 are connected with each other at a point, which is referred to as a node NetA.
Next, with reference to FIG. 8, the following will describe how the sensor circuit 10 having the above configuration operates.
During the sensor driving period, the data line 6′ is disconnected from the source driver 14, and is connected with the sensor read-out driver 17. At a time t1, which is the beginning of the sensor driving period, the voltage Vrst, which is applied to the reset wire RST by the sensor row driver 16, is set to a high level (here, 0V). This allows the photosensor D1 to become conductive in a forward direction, so that an electric potential VnetA at the node NetA is set to a high level (here, 0V). Further, at the time t1, the voltage Vpulse1, which is applied to the row selection wire RS by the sensor row driver 16, is set to a low level (here, 0V). The voltage Vdd, which is applied to the data line 6′ by the sensor read-out driver 17, is set to 15V which is a direct-current voltage.
Subsequently, at a time t2, the sensor row driver 16 sets the voltage Vrst to a low level (here, −10V). At the time t2, the photosensor D1 is put into an inverse-bias state, since an electric potential at the anode A becomes lower than that at the cathode K.
From the time t2, a charging period T1 begins. In the charging period T1, the node NetA is charged according to an intensity of light emitted to the photosensor D1. When light is emitted to the photosensor D1, an amount of a leakage current flowing from the cathode K to the anode A changes according to the intensity of the emitted light. In a light part, the amount of leakage current is large; therefore, an electric potential at the anode A, i.e., the electric potential VnetA is reduced rapidly. On the other hand, in a dark part, the amount of leakage current is small; therefore, the electric potential VnetA is reduced slowly.
At a time t3, at which the charging period T1 ends, the sensor row driver 16 sets the voltage Vpulse1 to a high level (here, 20V). In response to this, the electric potential VnetA is boosted from a negative electric potential to a positive electric potential, due to capacitive coupling by the capacitor C1, and an electric potential difference between the light part and the dark part is maintained. At the time t3, the amplifier TFT M1 becomes conductive; however, the electric potential VnetA, i.e., the electric potential at the gate of the amplifier TFT M1 is boosted, due to a bootstrap effect through capacitive coupling between the capacitor Cagd and the capacitor Cags. Consequently, the amplifier TFT M1 outputs, from the source, an output voltage Vout which is higher than that obtained in a case where no bootstrap effect is given. From the time t3, an output period T2, which is for sensor output, begins.
Here, assume that a total capacitor value Ctotal is expressed by:Ctotal=Cdgs+Cst+Cagd+Cags 
(each capacitor value in the right-hand side is indicated by a name of the corresponding capacitor), andα=Cst/Ctotal.Then, a boost value ΔVnetA, which is a value by which the electric potential VnetA is boosted by the voltage Vpulse1, is expressed by:ΔVnetA=α×Vpulse1p-p.Note that “Vpulse1p-p” represents a peak-to-peak voltage of Vpulse1. In the above example, Vpulse1p-p is 20V.
The output voltage Vout has a value corresponding to the electric potential VnetA. Therefore, by reading the output voltage Vout by the sensor read-out driver 17 in the output period T2, it is possible to detect the sensor output of the photosensor D1, i.e., the intensity of the light emitted to the photosensor D1.
At a time t4, at which the output period T2 ends, the sensor row driver 16 sets the voltage Vpulse1 to a low level (here, 0V). Thus, the sensor driving period ends.
Citation List
[Patent Literature]
    [Patent Literature 1]    International Publication, No. WO 2007/145347 (Publication Date: Dec. 21, 2007)    [Patent Literature 2]    Japanese Patent Application Publication, Tokukai, No. 2005-217708 A (Publication Date: Aug. 11, 2005)    [Patent Literature 3]    Japanese Patent Application Publication, Tokukaihei, No. 11-26740 A (Publication Date: Jan. 29, 1999)